The invention is directed to the field of superconducting Josephson junctions and, more particularly, to a high-temperature superconductive-superconductive-normal-superconductive (SSNS) Josephson junction and a high-temperature superconductive-normal-superconductive (SNS) Josephson junction and a method of making the junctions.
High-temperature superconductive (HTS) materials have a normal-to-superconducting transition temperature, T.sub.c, of more than 25 K. At lower temperatures, these materials exhibit no resistance to electrical current flow. High-T.sub.c superconductive materials are used in HTS circuits. In comparison to low-temperature superconductive (LTS) circuits, HTS circuits operate at significantly higher temperatures, typically about 25-100 K as compared to about 4-10 K for LTS circuits. HTS circuits are highly advantageous as compared to LTS circuits due to their relatively reduced cooling and insulation requirements.
HTS circuits can be used in a wide range of defense, industrial and commercial applications. HTS circuits can be used in analog-to-digital (ADC) applications such as analog signal processors (ASP), digital signal processors (DSP), high-speed computers, asynchronous transfer mode (ATM), switching networks, telecommunications, commercial satellites; rf applications such as resonators, band-pass filters, phased-array antennae for cellular/satellite telecommunications; and sensors such as magnetic sensors for mine-detection, anti-submarine warfare, and bio-magnetic diagnostic and non-destructive magnetic sensors.
HTS circuits are a vital next generation technology capable of replacing existing semiconductor technologies and having a tremendous growth potential within the next decade.
Despite providing important advantages, known HTS circuits have performance limiting problems as well. One basic problem of HTS circuits is the non-uniformity of the active devices. The basic active device used in HTS circuits is the Josephson junction. A key junction technology is the SNS Josephson junction. SNS Josephson junctions include two superconductive layers and an intermediate barrier layer (N layer) comprised of a normal material. During operation, a supercurrent flows through the barrier layer via the Josephson tunneling effect.
In known ramped high-T.sub.c SNS Josephson junctions, the SNS junction is formed by depositing the normal barrier layer and a high-T.sub.c superconductive counterelectrode layer on a ramped high-T.sub.c superconductive base electrode. One of the performance-limiting problems associated with known ramped SNS junctions is the occurrence of interfacial electric resistance at the base electrode/normal barrier layer interface at the ramp edge. This interfacial resistance is the result of the conventional fabrication process used to form the junction. Particularly, the base electrode is exposed to ambient conditions and to chemical treatments during the patterning process. As a result, the top several monolayers of the base electrode are degraded and deoxygenated, reducing the quality of these monolayers as compared to the bulk of the layer, and producing a resistive and/or non-uniform interface.
A resistive and/or non-uniform junction interface adversely affects process quality control by increasing the non-uniformity of the junction characteristics.
A technique that has been used in an attempt to overcome the problem of interfacial resistance in SNS junctions is low-energy ion-etch cleaning of the interface surface, either ex-situ before depositing the normal barrier layer and the counterelectrode layer, or, alternately, in-situ in the same vacuum system in which the barrier layer and counterelectrode layer are deposited. Ion-etch cleaning invariably also produces lattice damage in the exposed ramp edge of the base electrode, adversely affecting the interfacial electrical properties. Thus, this technique has not overcome the problem of interfacial resistance between the base electrode and the normal barrier layer in known SNS junctions.
A known technique of fabricating high-V.sub.c SNS Josephson junctions in-situ employs shadow masking. Particularly, a shadow mask is patterned on the substrate, and the base electrode is deposited by orienting a source at an angle relative to the shadow mask to form the ramp edge. The substrate is then rotated, and the barrier layer and the counterelectrode layer are deposited with the source oriented at a vertical angle relative to the substrate. The shadow mask is then removed.
This technique has proven less than satisfactory because the steps for forming the ramp edge are directional dependent and, so, junctions cannot be fabricated in an arbitrary direction of the substrate. This factor is a major limitation in integrated circuit process technology. In addition, the substrate cannot be rotated during the deposition process; consequently, the thickness of each of the deposited layers can vary significantly across the substrate. This non-uniformity is particularly severe in off-axis sputtering techniques which form a thickness gradient across the substrate unless the substrate is rotated, or unless special techniques are employed to randomize material deposition across the substrate.
Thus, there is a need for an improved high-T.sub.c Josephson junction that (i) overcomes the problem of electrical resistance at the base electrode/normal barrier layer interface and preserves the quality of the interfaces between the normal barrier layer and the adjacent superconductive layers; (ii) provides enhanced junction I.sub.c, and enhanced junction V.sub.c uniformity; and (iii) can be formed by a non-directional dependent process.